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Computer Engineering II

Exam details

Questions:

Attempt any 4 questions from 6

Time:

3 hours

Location:

Wed 06 June 2001 , 1300 - 1600, Craiglockhart [Link]

Exam coverage

The following defines the coverage of FOUR of the SIX questions in the Computer Engineering II exam (the other TWO are set by A.Armitage):

1. Cache Architecture (Chapter 5)

No:
Description
Section
1.1
Understands the basic architecture of a cache
5.4
1.2
Defines the different types of cache architures
5.4.1
1.3
Understands the requirements for cache coherency and snooping
5.4.2
1.4
Defines the requirements for the MESI protocol
5.4.7
1.5
Outlines the architecture of a basic cache system, showing cache directory and memory entries
5.4.4
1.6
Defines the requirements for each of the states of the MESI protocol
5.4.7

2. Memory (Chapter 12)

No:
Description
Section
2.1
Understands the basic architecture of DRAM, and the associated interface lines.
12.2
2.2
Outlines the method used to address DIMMs
12.2
2.3
Outlines the signal differences between SDRAM and EDO
Table 12.1
2.4
Defines how the access time of DRAM varies, such as the definition of 5-2-2-2.
12.2
2.5
Outlines the differences between different types of DRAM, such as EDO, SRAM, FPM and SDRAM.
12.2.1, 12.2.2, 12.2.3
2.6
Defines the timing requirements for acessing memory
 
2.7
Understands and defines the architecture of Direct RDRAM.
12.2.5

3. SCSI bus (Chapter 20)

No:
Description
Section
3.1
Outlines the main types of SCSI and their performance
To be updated
3.2
Identifies the main SCSI data and signal lines
 
3.3
Identifies the main SCSI data and signal lines
 
3.4
Describes the importance and usage of ID numbers of the SCSI bus
 
3.5
Describes how arbitration occurs on the SCSI bus
 
3.6
Describes the main phases that occur on the SCSI bus
 
3.7
Understands the importance of time-outs on the SCSI bus
 

4. PCI bus (Chapter 18)

No:
Description
Section
4.1
Explains the basic operation of the PCI bus
18.2
4.2
Explains multiplexed and burst modes of the PCI bus
18.2
4.3
Derives the maximum throughput for multiplexed and burst modes of the PCI bus
 
4.4
Identifies the main data and handshaking signals on the PCI bus
Table 18.1, 18.12
4.5
Identifies the main PCI bus cycles and how they are identified
 
4.6
Outlines the concept of bus mastering and how PCI uses it
 
4.7
Outlines the usage of the PCI command cycle
18.8
4.8
Outlines how bus arbitration and device locking is achieved on the PCI bus
18.3

5. Motherboard/Hub-based (Chapter 27 and 28)

No:
Description
Section
5.1
Identifies the main data, address and control signals used by the Pentium to communicate with other devices.
To be updated
5.2
Outlines the architecture of a north/south bridge system, identifying the main handshaking lines
 
5.3
Contrasts different Intel chipsets (440/450 and 810/820/840)
Table 28.1
5.4
Outlines the architecture of a hub-based system (especially the 810/820/840 chipset)
28.1, 28.2, 28.3
5.5
Contrasts north/south bridge architecture with hub-based systems, and identifies typical transfer rates for interfaces (such as IDE, AGP, PCI, and so on).
 

 



General

Main page

[Motherboard]
[Hub based]
[Cache systems]
[Memory]
[PCI]
[SCSI]
[AGP]

Notes

 

[Hub-based]
[Memory]
[PCI]
[SCSI]
[AGP]

Presentations

 

[1999/2000] [Ans]
[2000/2001] [Ans]

Past papers

 

[TCP/IP]
[
RS232]

Source code

 

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